Low power design of nanometer FPGAs: (Record no. 1055)
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|---|---|
| fixed length control field | 02245nam a2200205Ia 4500 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20210125110039.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 160802s9999 xx 000 0 und d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9780123744388 |
| 041 ## - LANGUAGE CODE | |
| Language code of text/sound track or separate title | eng |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.395 |
| Item number | HAS-L |
| 100 ## - MAIN ENTRY--AUTHOR NAME | |
| Personal name | Hassan, Hassan |
| 245 ## - TITLE STATEMENT | |
| Title | Low power design of nanometer FPGAs: |
| Remainder of title | architecture and EDA / |
| Statement of responsibility, etc | by Hassan H |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Name of publisher | Elsevier, |
| Year of publication | 2010. |
| Place of publication | Amsterdam: |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | xiv, 241 p. |
| 490 ## - SERIES STATEMENT | |
| Series statement | Morgan Kaufmann series in systems on silicon. |
| 505 ## - FORMATTED CONTENTS NOTE | |
| Formatted contents note | 1.FPGA Architectures --<br/>2.Power Consumption in Nanometer FPGAs --<br/>3.Power Modeling and Estimation Techniques in FPGAs --<br/>4.Dynamic Power Reduction --<br/>5.Leakage Power Reduction --<br/>6.Low-Power FPGA Design in Future CMOS Technologies. |
| 520 ## - SUMMARY, ETC. | |
| Abstract, etc | <br/>Field Programmable Gate Arrays (FPGAs) have become very popular as embedded components on computing platforms. An FPGA is a viable, reprogrammable design approach that provides a fast time-to-market alternative to Application Specific Integrated Circuits (ASICs). Since FPGA implementations can be customized to fit for any application, their versatility leads to performance gains, and enables reuse of expensive silicon. Although high performance can be achieved in FPGAs, their high levels of power consumption pose a critical design challenge. This book will be an invaluable reference for researchers and practicing engineers concerned with power-efficient, FPGA design. State-of-the-art power reduction techniques for FPGAs will be described and compared. These techniques will be applied at the circuit, architecture, and electronic design automation levels to describe both the dynamic and leakage power sources and enable strategies for codesign. Design perspective on low-power FPGAs ... low-power techniques presented at key FPGA design levels for circuits, architectures, and electronic design automation, form critical, "bridge" guidelines for codesign; Low-leakage design in FPGAs ... comprehensive review of leakage-tolerant techniques empowers designers to minimize power dissipation; FPGA power estimation techniques ... provides valuable tools for estimating power efficiency/savings of current, low-power FPGA design techniques. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | AR |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | Books |
| Lost status | Damaged status | Collection code | Home library | Current library | Shelving location | Date acquired | Source of acquisition | Cost, normal purchase price | Full call number | Accession Number | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Non Fiction | Library, SPAB | Library, SPAB | G-2 | 02/08/2016 | 001449621.395 HAS-L 00000133 20110922 29542 20100327 SEGMEN USD00009995 SPAB/LIB/2009-10/B | 2200.50 | 621.395 HAS-L | 001449 | Books |